Pinout diagram for I/O expansion port on back of 850 Interface
The text below lists the output pins for the Expansion Port on the back of the UI-5000 850 Universal Interface.
UI-5000 External I/O Definitions
These signals are on the 44-pin female HD Dsub connector. There is ESD protection for all signals but shorting power supply pins or signal generator pins to digital pins will cause damage, therefore external modules connected to this bus must provide the proper protection.
Looking at the connector, the top row, the right pin is 1 and the left pin is 15. The middle row right pin is 16 and the left pin is 30. The bottom row right pin is 31 and the left pin is 44. These are marked on the connector.
1-8 Data(0:7), respectively, independent I/O pins. All can be either 3.3V or 5V logic level.
9 SCLK, SPI clock from CPU. Normal Pasport interface but 3.3V logic level.
10 MISO, SPI data: Master In, Slave Out.
11 MOSI, SPI data: Master Out, Slave In.
12 SSn, SPI Slave Select, active low.
13 INTRn, SPI Interrupt, active low (handshake).
14 +5V @ 1A (assuming Pasport and CI sensors not all drawing max current, else 700mA).
15-28 System ground
29 Analog Input 1, inverting, +-10V limit. Slew rate = 1.2V/us, large signal BW ~ 21kHz.
30 Analog Input 1, non-inverting, +-10V limit.
31 Analog Input 2, inverting, +-10V limit. Slew rate = 1.2V/us, large signal BW ~ 21kHz.
32 Analog Input 2, non-inverting, +-10V limit.
33 Analog Input 3, inverting, +-10V limit. Slew rate = 1.2V/us, large signal BW ~ 21kHz.
34 Analog Input 3, non-inverting, +-10V limit.
35 Signal Generator 2 output.
36 Signal Generator 2 return (ground).
37 Signal Generator 3 output.
38 Signal Generator 3 return (ground).
39 +12V @ 150mA.
40 -12V @ 150mA.
41-42 Signal Generator 1 output.
43-44 Signal Generator 1 return (ground).
Creation Date: 04/15/2014
Last Modified: 04/15/2014